In earlier generations of microprocessor based chip sets, and more particularly those chip sets for those personal computers commonly known as PC/AT architectures, the range of CPU and DRAM speed was more narrow than available with current generations. Chip set designers were making designs to support 80286 microprocessors operating from 6 to 12 MHz. Such systems typically supported affordable dynamic memories with access times of approximately 120 or 100 nanoseconds (ns). Newer technologies have made available 80286 microprocessors operating at up to 25 MHz and 80386DX processors capable of 33 MHz clock rates. DRAM performance has also improved and some current DRAMs have access times as low as 50 ns. These new, faster devices have segregated the chip market between high-, mid-range- and lo-end personal computer systems, creating a need for a device that supports multiple user-programmable DRAM interface options.
Some prior art devices included programmable DRAM controllers which allowed the programmer limited interface options. However, most such DRAM controllers, when operating in a normal read or write mode, required a TCSH specification (minimum CAS asserted hold time relative to RAS asserted start time) and a TRSH specification (minimum RAS asserted hold time relative to CAS asserted start time). Typically, the TCSH DRAM specification is equivalent to the TRAS DRAM specification (minimum RAS asserted time) and if the TCSH specification is violated, the data transfer is unreliable. The DRAM specification could theoretically be violated if, for example, RAS was programmed to meet the TRAS DRAM specification and the minimum RAS asserted to CAS asserted delay time (TRCD DRAM specification) plus the minimum CAS asserted time (TCAS DRAM specification) was less than the total TCSH minimum time. Likewise, the TRSH specification could theoretically be violated if the RAS deassert time occurred before the CAS assert time (if the TRAS time programmed has been less than or equal to the TRCD time programmed) or if the test time programmed does not allow CAS to assert until after RAS assertion time has ended.
Thus a need exists for a device which will allow a range of RAS, CAS and related signals high and low pulse widths and start times to be programmed independently, effectively and correctly. The present invention is directed to fulfill that need by providing independent programming of RAS and CAS to meet the necessary wide range of CPU/DRAM combinations in today's chipset market. The unexpectedly efficient programming of the required DRAM parameters is obtained by minimizing the number of parameters needed to program by satisfying implicitly the TCSH and TRSH DRAM specifications which are based on other programmed values for DRAM specifications such as TRAS, TCAS and TRCD.